How to design a 4MB external memory with only 20 address bus lines on processor?

With 20 address lines you can only access a memory space of 1MB. You would need to use paged memory - basically swapping an area of memory for different pages (memory blocks), but if you do this then you must keep the system software out of this space to avoid crashes, or at least arrange the system software to expect the pages to be swapped. This system has been used on many computers, such as the ZX Spectrum 128K, Amstrad CPC6128 and various other later 8 bit machines with 16 bit address buses. How you decode it would depend on how much of the memory you need to be swappable. The simplest is to have 512kB permanently accessible and the other 512kB swappable - that way you'd only have to use line A19 to access that space, decoding would be simply a case of seeing if A19 has a 1 or a 0 on it, and if it's a 1 then the memory selection could be via a set of latches that have been set via one of the I/O ports - these need to be decoded too. These latches (3 bits of memory) would only need to hold three bits, since there would be seven blocks to switch (the lower 512k block being fixed) - the contents of those latches would be used to control the memory's top three address lines (A19 - A22). Obviously you don't have to use a 512kB page but a smaller page will require a little more decoding, but the principle is the same. Of course this is all theoretical/guesswork from my viewpoint, it's been about 25 years since I took a soldering iron to my TRS-80 to add extra features - you'd have to work out the details yourself in case I'm not quite right - for example if you use dynamic memory then you'll have to do something about the memory refresh for the switched out blocks. However, there are static memory chips available these days that are more than fast enough to cope with that processor - no memory refresh is required, so a much simpler design.